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? summit microelectronics, inc. 2000 ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378-6461 fax 408-378-6586 www.summitmicro.com 1 characteristics subject to change without notice 2041 8.4 6/15/00 smh4803 features ? supply range 20vdc to >500vdc versatile card insertion detection supports both ? multi-length pin systems ? card injector switch sensing control up to four loads or a primary load and 3 dc/dc converters highly programmable host voltage monitoring ? programmable under- and over-voltage detection programmable power good delays for sequencing dc/dc converters distributed power hot-swap controller programmable circuit breaker function ? programmable over-current filter ? programmable quick-trip ? circuit breaker values ? programmable circuit breaker mode duty-cycle mode latched mode 2.5v and 5.0v reference outputs ? easy expansion of external monitor functions functional block diagram associate member p r o g r a m m a b l e q u i c k - t r i p tm c i r c u i t b r e a k e r f eaturing + - + - + - 12v 5v 2.5v programmable delay programmable delay + - + - cbfault# 2041 bd 8.0 vgate 2.5v ref 5.0v ref pg1# pg2# enpgb enpga pg3# cbsense programmable delay vss cbmode cbreset# en/ts pd1# pd2# uv ov drain sense vdd fault latch & duty cycle timer + - 50 mv programmable quick-trip ref voltage filter 12v ref 12v current limit vgate sense 50k ? 50k ? 50k ?
2 smh4803 2041 8.4 6/15/00 summit microelectronics symbol pin description drain sense 1 drain sense input vgate 2 output to mosfet gate en/ts 3 enable/temp sense input pd1# 4 pin detect 1 (active lo) pd2# 5 pin detect 2 (active lo) cbfault# 6 circuit breaker fault output cbreset# 7 circuit breaker reset intput cbmode 8 circuit breaker mode control cbsense 9 cicruit breaker sense input vss 10 negative supply connection uv 11 under voltage input ov 12 over voltage input 5v 13 5v reference output 2.5v 14 2.5v reference output enpgb 15 enable input b enpga 16 enable input a pg3# 17 power good output 3 pg1# 18 power good output 1 pg2# 19 power good output 2 vdd 20 positive supply connection 2041 pgm t2.1 pin configurations recommended operating conditions condition min max temperature -40 c +85 c 2041 pgm t3.0 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 11 19 20 17 18 2041 ill10.1 drain sense vgate en/ts pd1# pd2# cbfault# cbreset# cbmode cbsense vss vdd pg2# pg1# pg3# enpga enpgb 2.5v 5v ov uv description the smh4803 is designed to control hot swapping of plug-in cards operating from a single supply ranging from 20v to 500v. the smh4803 hot-swap controller provides under-voltage and over-voltage monitoring of the host power supply, it drives an external power mosfet switch that connects the supply to the load, and also protects against over-current conditions that might disrupt the host supply. when the input and output voltages to the smh4803 controller are within specification, the smh4803 provides three ? power good ? logic outputs that may be used to turn on the loads, e.g. isolated-output dc- dc converters, or drive led status lights. the smh4803 provides three separate ? power good ? logic outputs that activate loads in a timed sequence. additional features of the smh4803 include: temperature sense or master en- able input, 2.5v and 5v reference outputs for expanding monitor functions, two ? pin-detect ? enable inputs for fault protection, and duty-cycle or latched over-current protec- tion modes.
3 2041 8.4 6/15/00 smh4803 summit microelectronics *comment stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this speci- fication is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. absolute maximum ratings temperature under bias -55 c to +125 c storage temperature -65 c to +150 c voltage on pins with respect to v ss vdd -0.5v to vdd uv, ov, cbsense, drain sense -0.5v to vdd +0.5v pd1#, pd2#, cbmode, cbreset# 10v enpga, enpgb, en/ts cbfault#, pg1#, pg2#, pg3# -0.5v to vdd +0.5v vgate vdd + 0.5v lead solder temperature (10 secs) 300 c symbol parameter notes min. typ. max. units v dd supply voltage i dd = 2ma 11 12 13 v vref5 5volt reference output i dd = 2ma 4.75 5 5.25 v i load5 5volt reference output current i dd = 2ma -1 1 ma vref2.5 2.5 volt reference output t a = 25 c, i dd = 2ma 2.475 2.5 2.525 v vref2.5 2.5 volt reference output i dd = 2ma 2.425 2.5 2.575 v i load2.5 2.5 volt reference output current i dd = 2ma -0.2 1 ma i dd power supply current output enabled 2 10 ma v uv under voltage threshold t a = 25 c, i dd = 2ma 2.475 2.5 2.525 v v uv under voltage threshold i dd = 2ma 2.425 2.5 2.575 v v uvhys under voltage hysteresis i dd = 2ma 10 mv v ov over voltage threshold t a = 25 c, i dd = 2ma 2.475 2.5 2.525 v v ov over voltage threshold i dd = 2ma 2.425 2.5 2.575 v v ovhys over voltage hysteresis i dd = 2ma 10 mv v vgate vgate output voltage v dd v i vgate vgate current output 100 a v sense drain sense threshold t a = 25 c, i dd = 2ma 2.475 2.5 2.525 v v sense drain sense threshold i dd = 2ma 2.425 2.5 2.575 v i sense drain sense output current (note 1) v sense = v ss 91011a v cb circuit breaker threshold i dd = 2ma 40 50 60 mv v qcb quick-trip circuit breaker threshold option e 200 mv option f 100 mv option h 50 mv option j off v ents en/ts threshold t a = 25 c, i dd = 2ma 2.425 2.5 2.575 v v ents en/ts threshold i dd = 2ma 2.475 2.5 2.525 v v entshys en/ts hysteresis i dd = 2ma 5 10 15 mv v ih input high voltage enpga/b, 2 vref5 v cbmode, cbreset# v il input high voltage enpga/b, -0.1 0.8 v cbmode, cbreset# v ol cbfault# output low voltage i ol = 2ma 0 0.4 v v ol pg1#, pg2#, pg3# output low i sink = 2ma 0 0.4 v dc operating characteristics (over recommended operating conditions, voltages are relative to v ss ) 2041 pgm t4.4 (note 1) : t a = 25 c
4 smh4803 2041 8.4 6/15/00 summit microelectronics ac timing characteristics, -40 o c to +85 o c symbol description min. typ. max unit t pdd pin detect delay to vgate enable 80 ms t cbd 50mv circuit breaker delay (filter) k 400 s l 150 s m50s n5s p gd power good delay (pg1/pg2, pg2/pg3) a5ms b20ms c80ms d 180 ms t fstshtdn fast shut down delay from fault to 200 ns vgate off t cyc circuit breaker cycle mode cycle time 2.5 sec. t vgd delay from release of reset to vgate on 100 ns t cbrst cbreset# pulse width 200 ns
5 2041 8.4 6/15/00 smh4803 summit microelectronics 11v 13v 2.5v ref 2.5v ref vdd uv ov pd1#/pd2# t pdd vgate 2.5v ref drain sense 50mv ref cbsense pg1# enpga pg2# enpgb pg3# 6 smh4803 2041 8.4 6/15/00 summit microelectronics figure 2. circuit breaker timing - cycle mode, cbreset# held high cbmode cbsense vgate cbreset# v ih t cbd t cyc t cbd v ih 50mv 2041 ill16.0 figure 3. circuit breaker timing - cycle mode, used to enable vgate cbmode cbsense vgate cbreset# v ih t cbd v il t cyc 50mv 2041 ill17.0
7 2041 8.4 6/15/00 smh4803 summit microelectronics figure 4. circuit breaker timing - reset mode figure 5. circuit breaker timing - quick-trip cbmode cbsense vgate cbreset# v il t cbd t cbrst t vgd 50mv 2041 ill14.0 cbsense vgate 8 smh4803 2041 8.4 6/15/00 summit microelectronics smh4803 pin descripiton pin name (pin #) drain sense (1) the drain sense input monitors the voltage at the drain of the external power mosfet switch with respect to v ss . when the mosfet is turned on, the drain sense input will be driven low and will be used as one of the enable conditions for the pg outputs. this will prevent any premature activation of the pg outputs. vgate (2) the vgate output activates an external power mosfet switch. it is a constant current source (100a typical) allowing easy programming of the mosfet turn on slew rate. en/ts (3) the enable/temperature sense input is the master en- able input. when en/ts is low, vgate, and the pg outputs are off. as the name suggests, the en/ts input may be used as a master enable by a host system or alternatively for circuit over-temperature protection using an external thermistor. pd1# and pd2# (4 & 5) the pin detect pins are active low inputs that are use to prevent any power sequence before the add-in card is properly seated. both inputs must be at v ss before either vgate or the pg outputs can be enabled. in applications where multi-length connector pins are use, the pd inputs should be tied to the short pins. on the mating connector side the pins opposite should be tied directly to v ss . alternatively, either one or both of the pd inputs can be tied to card injector handle switches, insur- ing no power sequencing will occur until the card is properly seated. cbfault# (6) cbfault# is an open drain active low output, indicating the circuit breaker status. when an over current condition is detected cbfault# is driven low. cbreset# (7) cbreset# is the circuit breaker reset input. it can be actively controlled to reset a fault condition or it can be tied high or low to allow either timed restarts (duty cycle mode) or ? latch-off ? the vgate output. refer to the circuit breaker operation and the associated timing diagrams for de- tailed characteristics. cbmode (8) the cbmode input selects one of two circuit breaker operational modes. when tied to v ss all fault conditions must be cleared by toggling the cbreset# input low then high. when cbmode is tied to 5v the circuit breaker will be placed in the self-restart or cycling mode. the state of cbreset# input will control the operation of the restart. if cbreset# is tied to 5v the vgate output will automatically restart after t cyc has elapsed. if the fault condition still exists, the circuit breaker will trip once again. the cycling will continue until the fault clears or the circuit board is replaced. alternatively the cbreset# input can be ac- tively driven to v ss . if a fault occurs the vgate and pg outputs will not be turned on again for t cyc after the cbreset# input is driven high. cbsense (9) the circuit breaker sense input is used to detect overcurrent conditions in the load connected to the power mosfet. a low value sense resistor (rs) is tied in series with the mosfet switch; one end tied to v ss and the other to the switch and the cbsense input. a voltage drop of greater than 50mv (for greater than t cbd ) across the resistor will result in the circuit breaker tripping. a pro- grammable ? quick-trip ? sense point is also available. if the cbsense input transitions above the threshold, the circuit breaker will immediately trip. v ss (10) v ss is connected to the negative side of the supply. uv and ov (11 & 12 ) the under-voltage (11) and over-voltage (12) input pins monitor the supply voltage for the smh4803 and the downstream circuits. both inputs have a 2.5v threshold on their respective comparators. if uv is less than 2.5v or if ov is greater than 2.5v, vgate will be disabled. 5.0v (13) 5.0v is a precision 5 volt output reference voltage tha may be use to expand the logic-input funtions on the smh4803. the reference output is with respect to v ss . 2.5v (14) 2.5v is a precision 2.5 volt output reference voltage tha may be use to expand the logic-input funtions on the smh4803. the reference output is with respect to v ss . enpgb (15) the enpgb input may be used to independently switch off the pg3# output. when enpgb is pulled low, the pg3# output is immediately placed in a high impedance state. if pg2# is active and enpgb is driven high, then the pg3# output will immediately be driven low.
9 2041 8.4 6/15/00 smh4803 summit microelectronics enpga (16) the enpga input controls the pg2# and pg3# outputs. when enpga is pulled low, the pg2# output is immedi- ately placed in a high impedance state. if enpga is driven high, then the pg2# output will immediately be driven low, provided pg1# has been active for at least t pgd . pg3# (17) pg3# is an open drain active low output with no internal pull-up. pg3# is the last power good signal to be enabled after vgate, pg1# and pg2# have been turned on. pg3# is delayed pg d after pg2# is active and 2xpg d after pg1# is active. pg3# can be used to switch a third load or a dc/dc converter. pg1# (18) pg1# is an open drain active low output with no internal pull-up. pg1# is enabled after vgate is enabled and voltage across the load is within spec. pg1# can be used to switch a load or enable a dc/dc converter. pg2# (19) pg2# is an open drain active low output with no internal pull-up. pg2# is enabled after vgate and pg1# have been turned on. pg2# is delayed pg d after pg1# is active. pg2# can be used to switch a second load or a dc/dc converter. v dd (20) v dd is the positive supply connection. an internal shunt regulator connected between v dd and v ss develops approximately 12 volts that supplies the smh4803. a resistor must be placed in series with the v dd pin to limit the regulator current (rd in the application illustrations). programmable features because the smh4803 is electrically programmable it can be fine-tuned for a wide variety of applications prior to shipment to the customer. because of this a manufacturer can use a common part type across a wide range of boards that are used on a common host but have different electrical loads, power-on timing requirements, host volt- age monitoring needs etc. this ability to use a common solution across many plat- forms shifts the focus of design away from designing a new power interface for each board to concentrating on the value added back-end logic. because the programming of the features is done at final test all combinations (all 128 possibilities) are readily available as off the shelf stock items. power good delay the pg delay timer that controls the delay from pg1# to pg2# and pg2# to pg3# being asserted can be set to typical values of 5ms, 20ms, 80ms or 160ms. quick-trip circuit breaker threshold the quick-trip circuit breaker threshold can be set to 200mv, 100mv, 60mv or off. this is the threshold voltage drop across r s that is placed between v ss and cbsense. circuit breaker delay the circuit breaker delay defines the period of time the voltage drop across r s is greater than 50mv but less than v qcb before the vgate output will be shut down. this is effectively a filter to prevent spurious shutdowns of vgate. the delays that can be programmed are 5s, 50s, 150s and 400s. pin detect the pin detect function can be enabled or disabled.
10 smh4803 2041 8.4 6/15/00 summit microelectronics device operation power-up sequence the smh4803 is an integrated power controller for hot swappable add-in cards. the device operates from a single supply ranging from 20v to 500v and generates the signals necessary to drive isolated output dc/dc con- verters. the smh4803 hot-swap controller provides under-volt- age and over-voltage monitoring of the host power sup- ply, it drives an external power mosfet switch that connects the supply to the load. it also protects against over-current conditions that might disrupt the host supply. when the input and output voltages to the smh4803 controller are within specification, the smh4803 provides three ? power good ? logic outputs that may be used to turn on loads or drive an led status light. the smh4803 provides three separate ? power good ? logic outputs that activate loads in a programmable timed sequence. there is a master enable/temperature sense input and 2.5v and 5v reference outputs for expanding monitor functions. there are two ? power good ? enable inputs that may be used to activate or deactivate output loads, and duty- cycle or reset over-current protection modes to provide automatic or manual restart of the controller after over- current load conditions. insertion process as the add-in board is inserted into the backplane, physi- cal connections must be made with the chassis to dis- charge any electrostatic voltage potentials. the board then contacts the long pins on the backplane that provide power and ground. as soon as power is applied the smh4803 starts up but does not immediately apply power to the output load. under-voltage and over-voltage cir- cuits inside the controller check to see if the input voltage is within a user-specified range, and pin detection signals determine whether the card is seated properly. t pdd after these requirements are met, the hot-swap controller enables vgate to turn on the power mosfet switch. the vgate output is current limited to i vgate , allowing the slew rate to be easily modified using external passive components. during the controlled turn-on pe- riod, the vds of the mosfet is monitored by the drain sense input. when vds drops below a user-specified voltage the power output is considered to be on. the resistor and diode in series with the drain sense input determine vds(on). provided there is no sustained over-current condition during start-up, the smh4803 turns on the loads with the power good logic outputs. three dc/dc converters can be connected to the outputs and their turn-on is sequenced by pre-programmed delays. if a sustained over-current condition occurs during or after the insertion process, then vgate is shorted to vss and the mosfet switch is turned off to protect the host supply. circuit breaker operation the smh4803 provides a circuit breaker function to protect against over current conditions. a sustained over- current event could damage the host supply and/or the load circuitry. the board ? s load current passes through a series resistor connected between mosfet source/ cbsense and vss on the controller. the breaker will trip whenever the voltage drop across the series resistor is greater than 50mv for more than t cbd , and will trip instantaneously if the voltage drop exceeds v qcb . when the breaker trips, the vgate output is turned off and cbfault# will be driven lo. the circuit breaker can be reset by taking cbreset# lo and then back hi when the circuit breaker is in the reset mode. in the duty-cycle mode, the circuit breaker resets automatically after a fixed time period. if the over current condition still exists after reset, the circuit will re-trip. in both operating modes of the circuit breaker, the mosfet can be switched off by holding the cbreset input lo. the value of the over-current shunt resistor is determined by the following formula: rs = 50mv/ i oc where rs is the value of the shunt resistor and i oc is the over current limit determined by the board ? s power requirement or the limit of the host supply. current sense resistors current sense resistors are available from a number of sources and come in two basic formats: open air sense resistors and current sense resistor chips. the open air resistors are metal strips that are available as both thru-hole and surface mount. the resistor chips are surface mount and offer excellent thermal characteristics. both styles are available in resistance ranges from 3 milliohm to 1 ohm. irc (www.irctt.com) is one source for these resistors. the open air sense resistors can be found in their oars series, and the chip resistors are found in their lrc series. load control the smh4803 is designed to control three or more dc/ dc converters, or other loads, which incorporate on/off control. the power good outputs activate the loads when the following conditions have been met: the input voltage to the smh4803 monitored by uv and ov is within user- defined limits and the external mosfet is switched on. the smh4803 has three power good enable outputs, pg1#, pg2#, and pg3#, that turn on the dc/dc con- verter loads in sequence. output pg1# is activated first, followed by pg2# after a delay of pg d , and finally pg3#
11 2041 8.4 6/15/00 smh4803 summit microelectronics after another delay pg d . the delays built into the smh4803 allow correct sequencing of power to the loads, e.g. +3v supply must come up before +5v supply. the delay times are factory programmed. pg2# and pg3# can be disabled using the enpga and enpgb inputs. when these inputs are low they override the enable function produced when the smh4803 sees a power good condition. the pg1#, pg2#, and pg3# outputs have a 12v with- stand capability so high voltages must not be connected to these pins. inexpensive bipolar transistors will boost the withstand voltage to that of the host supply, see figure 5 for connections. output slew-rate control the smh4803 provides a current limited vgate turn-on. a fast turn-off is performed by internally shorting vgate to vss. changing the passive components around the power mosfet switch will modify the turn-on slew-rate. operating at high voltages the breakdown voltage of the external active and passive components limits the maximum operating voltage of the smh4803 hot-swap controller. components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in series with drainsense pin, the power mosfet switch and capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller ? s vdd pin. over-voltage and under-voltage resistors in the following examples, the three resistors, r1, r2, and r3, connected to the ov and uv inputs must be capable of withstanding the maximum supply voltage which can be several hundred volts. the trip voltage of the uv and ov inputs is +2.5v relative to vss. as the input resis- tances of uv and ov are very high, high value resistors can be used in the resistive divider. the divider resistors should be high stability, 1% metal-film resistors to keep the under-voltage and over-voltage trip points accurate. telecom design example a hot-swap telecom application uses a 48v power supply with a ? 25% to +50% tolerance, i.e. the 48v supply can vary from 36v to 72v. the formulae for calculating r1, r2, and r3 are shown below. 1) first select the peak current, idmax, allowed through the resistive divider, say 250a. the value of current is arbitrary; however, if the current is too high, self- heating in r3 may become a problem (especially in high voltage systems), and if the current is too low the value of r3 becomes very large and may be expensive at 1% tolerance. r1 is calculated from: r 1 = vov is the over-voltage trip point, i.e. 2.5v, therefore: r 1 = =10k ? 2) the minimum current that flows through the resistive divider, idmin, is easily calculated from the ratio of maximum and minimum supply voltages: id min = therefore: id min = = 125 a 3) the value of r3 is now calculated using idmin. r 3 = where vuv is the under-voltage trip point, also 2.5v, therefore: r 3 = = 268k ? the closest standard 1% resistor value is 267k ? 4) r2 may be calculated using: (r 1 + r 2) = r 2 = ? r 1 or r 2 = ? 10k ? = (20k ? ? 10k ? ) = 10k ? vuv id min vuv id min 2.5 v 125 a id max x vs min vs max 250 a x 36 v 72 v ( vs min ? vuv ) id min (36 v ? 2.5 v ) 125 a vov id max 2.5 v 250 a
12 smh4803 2041 8.4 6/15/00 summit microelectronics dropper resistor selection the smh4803 is powered from the high-voltage supply via a dropper resistor, rd. the dropper resistor must provide the smh4803 (and its loads) with sufficient oper- ating current under minimum supply voltage conditions, but must not allow the maximum supply current to be exceeded under maximum supply voltage conditions. the dropper resistor value is calculated from: rd = where vsmin is the lowest operating supply voltage, vddmax is the upper limit of the smh4803 supply voltage, idd is minimum current required for the smh4803 to operate, and iload is any additional load current from the 2.5v and 5v outputs and between vdd and vss. the min/max current limits are easily met using the dropper resistor except in circumstances where the input voltage may swing over a very wide range, e.g. input varies between 20v and 100v. in these circumstances it may be necessary to add an 11v zener diode between v dd and v ss to handle the wide current range. the zener voltage should be below the nominal regulation voltage of the smh4803 so that it becomes the primary regulator. mosfet v ds (on) threshold the drain sense input on the smh4803 monitors the voltage at the drain of the external power mosfet switch with respect to v ss . when the mosfet ? s v ds is below the user-defined value the switch is considered to be on. the v ds (on) is adjusted using the resistor, r t , in series with the drain sense protection diode. this protection or blocking diode prevents high voltage breakdown of the drain sense input when the mosfet switch is off . an inexpensive 1n4148 diode offers protection up to 100v. the v ds (on) threshold is calculated from: v ds = v sense ? ( i sense r t ) ? v diode ? ( i rs r s ) where v diode is the forward voltage drop of the protection diode, and i rs is the current flowing through the circuit breaker sense resistor r s . the v ds (on) threshold varies over temperature due to the temperature dependence of v diode and i sense . the calculation below gives the v ds (on) threshold under the worst case condition of +85 c ambient. using a 68k ? resistor for r t gives: v ds (on) threshold = 2.5v ? (15a x 68k ? ) ? v diode = 2.5 ? 1.0 ? 0.5 = 1.0v applications circuits reversing polarity of the power good outputs the open-drain power good outputs on the smh4803 are active lo. the output polarity may be changed to active hi, when required, with a minor circuit change around the high-voltage buffer transistor, see figure 6. the 1n4148 blocking diode must be included to prevent high-voltage damage to the smh4803. expanding enable/monitoring on the smh4803 the 2.5v reference and 5v outputs on the smh4803 make it easy to expand the number of enable or monitor- ing inputs. the circuit in figure 8 illustrates how a quad low-voltage comparator expands the en/ts input to four enable inputs. the comparators draw power from the 5v output on the smh4803 and use the 2.5v reference for the switching threshold. en1 to en4 inputs can accept either analog or cmos logic level signals between vss and +5v. the comparator outputs are anded together and drive the en/ts input. a 1m ? resistor adds hysteresis around the comparators to prevent oscillation near the trip point. ( vs min ? vdd max) ( idd + i load )
13 2041 8.4 6/15/00 smh4803 summit microelectronics figure 6. changing polarity of power good output pg1# smh4803 * 10 ? 1k ? 100 nf 10 nf 100 v d s g 20m ? rs vgate rt 68k ? 100k ? 47k ? 1n4148 100k ? + 100f 100v 100nf 100v ? 48v out pg3# pg2# pg1 0v 1n4148 cbsense vdd +12v wrt v ss vss rd = 10k ? ? 48v 100nf 15v v ss 2.5v 5v mmbta06lt1 r2 r3 r1 cbreset# pd2# cbmode cbfault# enpga enpgb en/ts pd1# 100nf 25v 0v uv pd1# pd2# enpga enpgb en/ts ov cbfault# cbmode drain sense pg2# pg3# pg1# 2041 was5.6 * 10 ohm resistor must be located as close as possible to the mosfet. 10k ? 10k ?
14 smh4803 2041 8.4 6/15/00 summit microelectronics figure 7. overtemperature shutdown on smh4803 +5v wrt v ss 1m lmv331 1k ntc 50k @t max 50k smh4803 20m ? rs vgate rt 68k ? 100k ? 100k ? 100k ? + 100f 100v 100nf 100v 0v out pg3# pg2# pg1# ? 48v 1n4148 cbsense vdd +12v wrt v ss vss +2.5v wrt v ss rd = 10k ? ? 48v 100nf 15v 10nf 100v 1k ? 100nf v ss 2.5v 5v mmbta06lt1 r2 r3 r1 cbreset# cbmode cbfault# enpga enpgb en/ts pd1# pd2# 100nf 25v 0v uv pd1# pd2# enpga enpgb ov cbfault# cbmode drain sense pg2# pg3# pg1# 2041 was6.6 * 10 ? * 10 ohm resistor must be located as close as possible to the mosfet. 10k ? 10k ?
15 2041 8.4 6/15/00 smh4803 summit microelectronics figure 8. expanding input monitoring capability +5v wrt v ss 1k ? lmv339 en1 en2 en3 en4 0v 1m ? 10k ? + ? + ? smh4803 20m ? rs vgate rt 68k ? 100k ? 100k ? 100k ? + 100f 100v 100nf 100v 0v out pg3# pg2# pg1# ? 48v 1n4148 cbsense vdd vss +2.5v wrt v ss rd = 10k ? ? 48v 100nf 15v 10nf 100v 1k ? 100nf v ss 2.5v 5v mmbta06lt1 r2 r3 r1 cbreset# cbmode cbfault# enpga enpgb en/ts pd1# pd2# 100nf 25v uv pd1# pd2# enpga enpgb en/ts ov cbfault# cbmode drain sense pg2# pg3# pg1# 2041 was7.5 + ? + ? * 10 ? * 10 ohm resistor must be located as close as possible to the mosfet. 10k ? 10k ?
16 smh4803 2041 8.4 6/15/00 summit microelectronics figure 9. typical application sequencing 3 dc/dc converters isolated dc/dc #3 ? 48v 3x mmbta06lt1 100k ? 100k ? 100k ? 0v v1 v2 isolated dc outputs v3 +12v rd = 10k ? ? 48v 0v rs r3 r2 r1 5v uv en/ts pd1# pd2# vdd enpgb enpga cbsense ov vss vgate pg3# pg2# drain sense pg1# smh4803 + 2041 was12.3 isolated dc/dc #2 isolated dc/dc #1 pd2# en/ts 100nf 25v pd1# * 10 ? * 10 ? resistor must be located as close as possible to the mosfet. 10k ? 10k ? ? 48v ? 48v
17 2041 8.4 6/15/00 smh4803 summit microelectronics figure 10. sequencing 3 dc/dc converters with output voltage feedback isolated dc/dc #3 0v v1 v2 isolated dc outputs v3 +12v rd +5v v1 reset1# reset2# ? 48v 0v rs r3 + 100nf 25v r2 r1 5v uv en/ts pd1# pd2# vdd enpgb enpga cbsense ov vss vgate pg3# pg2# drain sense pg1# smh4803 + 2041 iwas9.5 isolated dc/dc #2 isolated dc/dc #1 reset reset pd2# en/ts pd1# * 10 ? * 10 ? resistor must be located as close as possible to the mosfet. 10k ? 10k ? ? 48v ? 48v ? 48v
18 smh4803 2041 8.4 6/15/00 summit microelectronics figure 11. sequencing converters with common i/o ground and voltage feedback isolated dc/dc #3 v1 ov v2 v3 rd 47 k 47 k 47 k 47 k reset1# reset2# 2x1n4148 2x mmbta56lt1 ov ? 48v rs r3 100nf 25v r2 r1 5v uv en/ts pd1# pd2# vdd enpgb enpga cbsense ov vss vgate pg3# pg2# drain sense pg1# smh4803 + 2041 was11.3 isolated dc/dc #2 isolated dc/dc #1 reset reset 10 k pd1# pd2# 10 k * 10 * 10 ohm resistor must be located as close as possible to the mosfet. ? 48v ? 48v ? 48v
19 2041 8.4 6/15/00 smh4803 summit microelectronics 20-lead small outline package (soic) 0.014 - 0.019 (0.356 - 0.482) 0.004 - 0.012 (0.102 - 0.305) 0.037 - 0.045 (0.940 - 1.143 0.496 - 0.512 (12.598 - 13.005) 0.394 - 0.419 (10.007 - 10.643) 0.093 - 0.104 (2.362 - 2.642) 0.016 - 0.050 (0.406 - 1.270) 0.050 (1.270) 0.009 - 0.013 (0.229 - 0.330) 0.010 - 0.029 (0.254 - 0.737) 0.291 - 0.299 (7.391 - 7.595) 20pn soic ill.1 0 to 8 typ x45
20 smh4803 2041 8.4 6/15/00 summit microelectronics ordering information pin detect function blank = enabled p = disabled circuit breaker delay k = 400 s l = 150 s m = 50 s n = 5 s quick-trip threshold e = 200mv f = 100mv h = 60mv j = off base part number smh4803 aekp 2041 ill8.3 power good delay a = 5ms b = 20ms c = 80ms d = 160ms
21 2041 8.4 6/15/00 smh4803 summit microelectronics smh4803 a e k smh4803 c e k smh4803 a e l smh4803 c e l smh4803 a e m smh4803 c e m smh4803 a e n smh4803 c e n smh4803 aekp smh4803 c e k p smh4803 a e l p smh4803 c e l p smh4803 a e m p smh4803 c e m p smh4803 a e n p smh4803 c e n p smh4803 a f k smh4803 c f k smh4803 a f l smh4803 c f l smh4803 a f m smh4803 c f m smh4803 a f n smh4803 c f n smh4803 a f k p smh4803 c f k p smh4803 a f l p smh4803 c f l p smh4803 a f m p smh4803 c f m p smh4803 a h n p smh4803 c h n p smh4803 a h k smh4803 c h k smh4803 a h l smh4803 c h l smh4803 a h m smh4803 c h m smh4803 a h n smh4803 c h n smh4803 a h k p smh4803 c h k p smh4803 a h l p smh4803 c h l p smh4803 a h m p smh4803 c h m p smh4803 a h n p smh4803 c h n p smh4803 a j k smh4803 c j k smh4803 a j l smh4803 c j l smh4803 a j m smh4803 c j m smh4803 a j n smh4803 c j n smh4803 a j k p smh4803 c j k p smh4803 a j l p smh4803 c j l p smh4803 a j m p smh4803 c j m p smh4803 a j n p smh4803 c j n p smh4803 b e k smh4803 d e k smh4803 b e l smh4803 d e l smh4803 b e m smh4803 d e m smh4803 b e n smh4803 d e n smh4803 bekp smh4803 d e k p smh4803 b e l p smh4803 d e l p smh4803 b e m p smh4803 d e m p smh4803 b e n p smh4803 d e n p smh4803 b f k smh4803 d f k smh4803 b f l smh4803 d f l smh4803 b f m smh4803 d f m smh4803 b f n smh4803 d f n smh4803 b f k p smh4803 d f k p smh4803 b f l p smh4803 d f l p smh4803 b f m p smh4803 d f m p smh4803 b h n p smh4803 d h n p smh4803 b h k smh4803 d h k smh4803 b h l smh4803 d h l smh4803 b h m smh4803 d h m smh4803 b h n smh4803 d h n smh4803 b h k p smh4803 d h k p smh4803 b h l p smh4803 d h l p smh4803 b h m p smh4803 d h m p smh4803 b h n p smh4803 d h n p smh4803 b j k smh4803 d j k smh4803 b j l smh4803 d j l smh4803 b j m smh4803 d j m smh4803 b j n smh4803 d j n smh4803 b j k p smh4803 d j k p smh4803 b j l p smh4803 d j l p smh4803 b j m p smh4803 d j m p smh4803 b j n p smh4803 d j n p valid part number combinations
22 smh4803 2041 8.4 6/15/00 summit microelectronics notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc.

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